Method of forming a metal to polysilicon contact in oxygen environment

ABSTRACT

A method for forming a contact capable of tolerating an O 2  environment up to several hundred degrees Celsius for several hours is disclosed. To slow down the metal oxide front of the metal layer at the metal-polysilicon interface, the metal layer is surrounded by one or more oxygen sink spacers and layers. These oxygen sink spacers and layers are oxidized before the metal layer at the bottom of the plug is oxidized. Accordingly, the conductive connection between the polysilicon and any device built on top of the barrier layer is preserved.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductorintegrated circuits and, in particular, to metal-polysilicon contactscapable of tolerating high temperature oxidizing environments.

BACKGROUND OF THE INVENTION

[0002] Semiconductor integrated circuits with high device density poseincreasing difficulty to the formation of high-reliability electricalconnections between metalization layers and semiconductor elements,particularly between the metal of a metallic electrode and the adjacentpolysilicon of a polysilicon plug. This increased difficulty stemsmainly from the tendency of metal and silicon to interdiffuse when incontact with each other, and when subjected to the high temperaturesnecessary during the fabrication of integrated circuits.

[0003] To illustrate the tendency of metal-silicon interdiffusion, theformation of a metallic contact between a polysilicon plug and ametallic electrode at a specified contact area will be briefly describedbellow. FIG. 1 depicts a portion of a conventional memory cellconstruction for a DRAM at an intermediate stage of the fabrication, inwhich a metal-polysilicon contact is formed according to conventionalprocesses.

[0004] A pair of memory cells having respective access transistors 33are formed within a well 13 of a substrate 12. The wells and transistorsare surrounded by a field oxide region 14 that provides isolation.N-type active regions 16 are provided in the doped p-type well 13 ofsubstrate 12 (for NMOS transistors) and the pair of access transistorshave respective gate stacks 30. The gate stacks 30 include an oxidelayer 18, a conductive layer 20, such as poly silicon, nitride spacers32, and a nitride cap 22. Additional stacks 31 may also be formed foruse in performing self aligned contact etches to form conductive plugsfor capacitor structures in the region between stacks 30, 31. Thedetails of these steps are well-known in the art and are not describedin this application.

[0005] Next, a polysilicon plug 50 (FIG. 1) is formed in a contactopening of a first insulating layer 24, to directly connect to a sourceor drain region 16 of the semiconductor device. The first insulatinglayer 24 could be, for example, borophosphosilicate glass (BPSG),borosilicate glass (BSG), or phosphosilicate glass (PSG). Once thepolysilicon plug 50 is formed, the whole structure, including thesubstrate 12 with the gate stacks 30, the first insulating layer 24 andthe polysilicon plug 50, is chemically or mechanically polished toprovide a planarized surface.

[0006] At this point, a second insulating layer 25, which can be of thesame material as that of the first insulating layer 24, is depositedover the first insulating layer 24 and the polysilicon plug 50. Acontact opening or via is etched over the polysilicon plug 50 and ametal layer or metal electrode 55 is then deposited and patterned toconnect to the polysilicon plug 50, as illustrated in FIG. 1. Thus,polysilicon plug 50 comes into contact with the metal layer or electrode55 at a metal-polysilicon interface 51 (FIG. 1). It must be understood,however, that, as known in the art, any other conductor, such as acapacitor plate for example, may also be in contact with a polysiliconplug, and the discussion herein applies to any metal-polysiliconinterface.

[0007] Since several steps during the IC fabrication requiretemperatures higher than 500° C., such as annealing steps, for example,silicon from the polysilicon plug 50 migrates into the metal film of themetallic electrode 55 during these high-temperature steps. Although thissilicon migration into the metal film occurs in limited regions, near orat the metal-polysilicon interface 51, since the migrated silicon hashigh resistivity, the contact resistance at the metal-polysiliconinterface 51 is greatly increased.

[0008] Barrier layers have been introduced to solve the silicondiffusion problem at the metal-polysilicon contact, such as interface 51(FIG. 1). A barrier layer 52 is illustrated in FIG. 2 (which shows onlya middle portion of the structure of FIG. 1). Conventionally, thebarrier layer is a refractory metal compound such as refractory metalnitrides (for example TiN or HfN), refractory metal carbides (forexample TiC or WC), or refractory metal borides (for example TiB orMoB). Barrier layers suppress the diffusion of the silicon and metalatoms at the polysilicon-metal interface, while offering a lowresistivity and low contact resistance between the silicon and thebarrier layer, and between the metal and the barrier layer. However,there is a problem with such barrier layers in that, in an O₂ hightemperature environment, they oxidize and disconnect the metal layerfrom the polysilicon plug. The oxide of the barrier layer may be formedeither between the metal and the barrier layer, or between thepolysilicon and the barrier layer. The latter situation is illustratedin FIG. 3, which shows metal oxide layer 53 formed between barrier layer52 and polysilicon plug 50. In either case, the oxide of the barrierlayer affects the conductive properties of the metal contact byincreasing the electric resistance in the electrical connection region.

[0009] In an effort to reduce the oxidation problems posed by barrierlayers subjected to oxidizing environments, different techniques havebeen introduced into the IC fabrication. One of them is manipulating andcontrolling the deposition parameters of the barrier materials. Forexample, U.S. Pat. No. 4,976,839 discloses that the presence of an oxideat grain boundaries within a titanium nitride (TiN) barrier layerimproves the ability of the barrier layer to prevent the diffusion ofsilicon and aluminum. The reference further discloses a method forforming a barrier layer having large grain sizes by increasing thesubstrate temperature during sputtering, so that the formation of theoxide at the grain boundaries may be accomplished with a relativelylarge amount of oxygen, but without degradation in the filmconductivity.

[0010] Similarly, to further improve the characteristics of the barrierlayers, certain metals, for which both the oxidized species (MeO) aswell as the unoxidized species (Me) are electrically conducting, havebeen recently used as barrier layers between metal and polysilicon.Examples of these metals are ruthenium (Ru), platinum (Pt), or iridium(Ir), among others. Since these barrier layers are conductive in boththe metal and the oxide forms, this approach is useful in that both theoxide and the metal forms slow down the oxidation front in an O₂ hightemperature environment. However, this technique has a drawback in thatthere will still be some areas where the metal does not oxidize and,thus, the barrier layer would consist of portions of pure metal speciesand portions of metal oxide.

[0011] Accordingly, there is a need for an improved method for slowingdown the oxidation front in barrier layers used in contacts betweenmetal and polysilicon so that there is no oxidation at thepolysilicon-metal interface. There is also a need for metal-polysiliconcontacts that inhibit the diffusion of silicon and metal atoms at acontact interface and prevent the formation of oxides under hightemperature O₂ environment, as well as a method of forming suchmetal-polysilicon contacts.

SUMMARY OF THE INVENTION

[0012] The present invention provides a method for forming ametal-polysilicon contact that would be capable of tolerating an O₂environment up to several hundred degrees Celsius for several hours. Toprevent a metal oxide front, which is formed during a high temperatureO₂ treatment from reaching the metal film at the metal-polysiliconinterface, the metal film is surrounded by a plurality of oxygen sinks.These oxygen sinks are oxidized before the metal film at the bottom ofthe plug is oxidized. Accordingly, the conductive connection between thepolysilicon and any device built on top of the barrier layer ispreserved.

[0013] Additional advantages of the present invention will be moreapparent from the detailed description and accompanying drawings, whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a schematic cross-sectional view of a portion of aconventional memory DRAM device illustrating a metal-polysilicon contactformed in accordance with a method of the prior art.

[0015]FIG. 2 is a schematic cross-sectional view of the FIG. 1 deviceillustrating use of a barrier layer in a metal-polysilicon contactformed in accordance with the prior art.

[0016]FIG. 3 is a schematic cross-sectional view of the FIG. 2 devicedepicting the formation of an oxide layer between a polysilicon plug anda barrier layer.

[0017]FIG. 4 is a schematic cross-sectional view of a portion of amemory DRAM device, in which a metal-polysilicon contact according to afirst embodiment and method of the present invention will be formed.

[0018]FIG. 5 is a schematic cross sectional view of the FIG. 4 device ata stage of processing subsequent to that shown in FIG. 4.

[0019]FIG. 6 is a schematic cross sectional view of the FIG. 5 device ata stage of processing subsequent to that shown in FIG. 5.

[0020]FIG. 7 is a schematic cross sectional view of the FIG. 6 device ata stage of processing subsequent to that shown in FIG. 6.

[0021]FIG. 8 is a schematic cross sectional view of the FIG. 7 device ata stage of processing subsequent to that shown in FIG. 7.

[0022]FIG. 9 is a schematic cross sectional view of the FIG. 8 device ata stage of processing subsequent to that shown in FIG. 8.

[0023]FIG. 10 is a schematic cross sectional view of the FIG. 9 deviceat a stage of processing subsequent to that shown in FIG. 9.

[0024]FIG. 11 is a schematic cross sectional view of the FIG. 10 deviceat a stage of processing subsequent to that shown in FIG. 10.

[0025]FIG. 12 is a schematic cross sectional view of the FIG. 11 deviceat a stage of processing subsequent to that shown in FIG 11.

[0026]FIG. 13 is a schematic cross sectional view of the FIG. 12 deviceat a stage of processing subsequent to that shown in FIG. 12.

[0027]FIG. 14 is a schematic cross sectional view of the FIG. 13 deviceat a stage of processing subsequent to that shown in FIG. 13.

[0028]FIG. 15 is a schematic cross sectional view of the FIG. 14 deviceat a stage of processing subsequent to that shown in FIG. 14.

[0029]FIG. 16 is a schematic cross sectional view of the FIG. 15 deviceat a stage of processing subsequent to that shown in FIG. 15, anddepicting a capacitor formed over the metal-polysilicon contact.

[0030]FIG. 17 is a schematic cross sectional view of the FIG. 16 deviceat a stage of processing subsequent to that shown in FIG. 16.

[0031]FIG. 18 is a schematic cross sectional view of the FIG. 14 deviceat a stage of processing subsequent to that shown in FIG. 14, and inaccordance with a second embodiment of the present invention.

[0032]FIG. 19 is a schematic cross sectional view of the FIG. 14 deviceat a stage of processing subsequent to that shown in FIG. 14, and inaccordance with a third embodiment of the present invention.

[0033]FIG. 20 is a schematic cross sectional view of the FIG. 18 deviceat a stage of processing subsequent to that shown in FIG. 18, anddepicting a capacitor formed over the metal-polysilicon contact.

[0034]FIG. 21 is an illustration of a computer system having a memorydevice employing the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0035] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural, logical,and electrical changes may be made without departing from the spirit orscope of the present invention.

[0036] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposed siliconsurface. Structure must be understood to include silicon-on insulator(SOI), silicon-on sapphire (SOS), doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. The semiconductor neednot be silicon-based. The semiconductor could be silicon-germanium,germanium, or gallium arsenide. When reference is made to substrate inthe following description, previous process steps may have been utilizedto form regions or junctions in or on the base semiconductor orfoundation.

[0037] The present invention provides a method for forming a metaloxide-metal-polysilicon contact capable of tolerating on oxygenenvironment up to several hundred degrees and for several hours. Theinvention provides one or more oxygen sink layers, which are oxidizedbefore the metal film is oxidized at the metal-polysilicon interface.The oxygen sink layers slow down the oxidation front of the metal film,so it does not reach the metal-polysilicon interface.

[0038]FIG. 4 depicts a conventional memory cell construction for a DRAMat an intermediate stage of the fabrication, in which a pair of memorycells having respective access transistors are formed on a substrate 12.The FIG. 4 structure includes the substrate 12 having a well 13, whichis typically doped to a predetermined conductivity, e.g. p-type orn-type depending on whether NMOS or PMOS transistors will be formedtherein. The structure further includes field oxide regions 14,conventional doped active areas 16 for use as source/drain regions, anda pair of gate stacks 30, all formed according to well-knownsemiconductor processing techniques. The gate stacks 30 include an oxidelayer 18, a conductive layer 20, such as polysilicon, nitride spacers 32and a nitride cap 22.

[0039] Above the gate oxide region 18, tie polysilicon gates 20, and theprotective nitride regions 22, 32, a first insulating layer 24 (FIG. 4)is disposed. Insulating layer 24 could be, for example,borophosphosilicate glass (BPSG), borosilicate glass (BSG), orphosphosilicate glass (PSG).

[0040] Reference is now made to FIG. 5, which for simplicity illustratesonly a lateral portion, for example a right side portion, of FIG. 4.This is a region where a contact plug and an overlying capacitorstructure will be formed. To create a contact opening 40 (FIG. 6) intosemiconductor substrate 12 through the first insulating layer 24, aphotoresist material 26 (FIG. 5) is deposited and patterned usingconventional photolithography steps. After patterning, an initialopening 27 (FIG. 5) is present in photoresist layer 26 for subsequentoxide etching. The structure of FIG. 5 is then etched, to form a contactopening 40 through first insulating layer 24 and the photoresist layeris removed as shown in FIG. 6. The contact opening 40 is etched so thatcontact opening 40 extends to a source/drain region 16 provided in well13 of substrate 12.

[0041] Next, contact opening 40 is filled with a conductive material,such as doped polysilicon, that is planarized down to or near the planarsurface of the first insulating layer 24, to form a polysilicon plug orfiller 50, as illustrated in FIG. 7. The polysilicon plug 50 is thenanisotropically etched until its top surface is recessed below theplanar surface of the first insulating layer 24, so that a barrier layer52 (FIG. 8) can be deposited and planarized, as shown in FIG. 8. Thebarrier layer 52, preferably of titanium (Ti), is formed on thepolysilicon plug 50 by CVD, PVD, sputtering or evaporation, to athickness of about 60 to about 200 Angstroms. The titanium barrier layer52 will form titanium silicide (TiSi₂) during a later high temperatureanneal.

[0042]FIG. 9 illustrates the deposition of a second insulating layer 25,which could be, for example, a silicon oxide, borophosphosilicate glass(BPSG), borosilicate glass (BSG), phosphosilicate glass (PSG), ortetraethylorthosilicate (TEOS). The second insulating layer 25 isdeposited over the barrier layer 52 and the first insulating layer 24.Again, using the same fabrication technique as the one used for theformation of contact opening 40 (FIG. 6) through the first insulatinglayer 24, a contact opening 41 (FIG. 10) is formed through the secondinsulating layer 25.

[0043] Subsequent to the formation of contact opening 41 of FIG. 10, amaterial acting as an oxygen sink is deposited by using plasma, reactivesputtering or a conventional chemical vapor deposition to form a firstoxygen sink layer 60, as shown in FIG. 11, to a thickness of about 100Angstroms. Preferred materials for the first oxygen sink layer 60 arepolysilicon, aluminum nitride, titanium, titanium nitride, siliconnitride, or tantalum, among others. A characteristic of the sinkmaterial is that it oxidizes in a high temperature O₂ environment.Although some of the metals employed as oxygen sink oxidize and becometherefore nonconductive, this fact raises no problems because, in theembodiments described below, these metals are used strictly as oxygensinks and not as barrier layers. After deposition of the oxygen sinklayer 60, a spacer etch is employed to remove portions of the firstoxygen sink layer 60 inside the contact opening 41 and on the planarsurface of the second insulating layer 25, leaving only spacers 61formed of oxygen sink material on the side walls of contact opening 41,as illustrated in FIG. 12. The etch stops at the upper surface of thebarrier layer 52, without damaging, or etching into, the upper surfaceof the barrier layer 52.

[0044] Next, referring to FIG. 13, a layer 62 of conductive metal isformed inside the contact opening 41, over the upper surface of thebarrier layer 52, over the spacers 61 and over the upper surface ofinsulating layer 25. Although FIG. 13 illustrates the metal layer 62 asformed over the upper surface of the second insulating layer 25, it isto be understood that metal layer 62 does not have to cover the secondinsulating layer 25. Depending on the type of devices that would befurther built to complete the formation of a DRAM memory cell, the metallayer 62 may or may not extend over the second insulating layer 25, aslong as it is formed inside of the contact opening 41.

[0045] Preferred materials for the conductive material layer 62 aremetal conductors which, when oxidized, are still conductive, such asplatinum (Pt), ruthenium (Ru), iridium (Ir), rhodium (Rh) and theirrespective oxides, or any other metal capable of forming a metal-barrierlayer-polysilicon contact on top of the polysilicon plug or filler 50.Metal layer 62 could be formed by any conventional method, such asdeposition or sputtering, to a thickness of approximately 100 to 300Angstroms.

[0046] A second oxygen sink layer 64 is next formed over the metal ormetal oxide layer 62. This is illustrated in FIG. 14. The material forthis second oxygen sink layer 64 may be, for example, a material whichoxidizes at high temperature O₂ environment, such as polysilicon,aluminum nitride, titanium nitride, silicon nitride, or tantalum. Thesecond oxygen sink layer 64 is then chemically metal polished (CMP) toform oxygen sink layer 64 of FIG. 15, on top of which another devicecould now be built.

[0047] For example, as shown in FIG. 16, a capacitor 80 formed of afirst ruthenium oxide conductor (RuOx) layer 81, a tantalum oxidedielectric (TaOx) layer 82, and a second ruthenium oxide conductor(RuOx) layer 83 can be formed in an opening created in a thirdinsulating layer 27 provided over the second insulating layer 25, at aposition on top of the upper surface of the oxygen sink layer 64. TheRuOx layer 81 is fabricated to be in contact with metal (or metal oxide)layer 62. As known in the art, during the fabrication process of thecapacitor 80, the first ruthenium oxide conductor 81 requires an N₂/O₂anneal, in an oxygen environment at high temperatures. Thus, during theanneal step, an oxygen front will move through the first ruthenium oxideconductor 81, and move towards the oxygen sink layer 64, the metal layer62 and the barrier layer 52, towards the polysilicon plug 50, as shownin FIG. 17. The oxygen front will be delayed by the oxygen sink layers64 and 61, but will nevertheless start oxidizing the metal layer 62 fromthe top of the upper surface of the second insulating layer 25.

[0048] The oxygen sink layers 64 and 61 slow the movement of the oxygenfront so that it never reaches barrier layer 52 during the N₂/O₂ anneal.This is shown in FIG. 17. The upper portion of the metal layer 62 mayoxidize during the anneal process to form a conductive metal oxide layer62 a, but the remaining portion of the metal layer 62 is not oxidizedduring the anneal process as is shown by unoxidized metal layer 62 b.Thus, an effective conductive path from capacitor conductor 81 toconductive plug 50, through metal oxide layer 62 a, metal layer 62 b,and barrier layer 52, is provided.

[0049] As a general proposition, it should be clear that the thicker theoxygen sink layer 64, the slower the advancement of the oxygen fronttowards the barrier layer 52 and the polysilicon plug 50. Similarly, thegreater the number of oxygen sink layers, the slower the advancement ofthe oxygen front towards the barrier layer 52. Of course, as well-knownin the art, the advancement of the oxygen front toward the polysiliconplug 50 is also slowed down by employing a high aspect ratio contact,that is, a contact with a small cross section A (FIG. 17) but a largeheight L (FIG. 17) of the spacers 61 formed of oxygen sink material. Ahigh aspect ratio is, for example, an aspect ratio of 25. Thus, ideally,the oxygen front is delayed by employing a multi-layer oxygen sink in ahigh aspect ratio metal-polysilicon contact.

[0050]FIG. 18 shows a second embodiment of the invention, which uses afirst and second oxygen sink spacers, 61 and 71, respectively, as wellas a first and second metal layers, 62 and 72, respectively, formedbefore a first oxygen sink layer 64 is formed. Layers 62, 71, 72 and 64are sequentially formed in a way similar to that employed for theformation of metal layer 62 (FIG. 13) and oxygen sink layer 64 (FIGS.14-15), described with respect to the formation of the first embodimentof the present invention. As shown in FIG. 18, each of the layers 62,71, 72 and 64 is chemical mechanical polished (CMP) so that each oftheir upper surfaces end at the upper surface of the second insulatinglayer 25, where a capacitor structure can be built in the manner shownand described with reference to FIGS. 16 and 17. Of course, as explainedabove, layers 62, 71, 72 and 64 could extend over and cover the uppersurfaces of the second insulating layer 25, as long as the conductor 81of a fabricated overlying capacitor can connect with conductive layers62 and 72.

[0051]FIG. 19 illustrates yet a third embodiment of the presentinvention, which uses an oxygen sink layer that is not a good barrier tooxygen diffusion. An example of such oxygen sink material is titanium.In this embodiment, nitride layers 93, 95 and 97 formed of siliconnitride, for example, which is a good oxygen barrier, is used inconnection with titanium oxygen sink spacers 61 and 71, and titaniumlayer 64. As explained above, the first and second oxygen sink spacers,61 and 71, formed of titanium, as well as a first and second metallayers, 62 and 72, respectively, are formed before the titanium layer 64is formed. Layers 93, 62, 95, 71, 72, 97 and 64 are sequentially formedin a way similar to that employed for the formation of metal layer 62(FIG. 13) and oxygen sink layer 64 (FIGS. 14-15), described with respectto the formation of the first embodiment of the present invention. Asshown in FIG. 19, when all of the layers 93, 62, 95, 71, 72, 97 and 64are applied, the structure is chemical mechanical polished (CMP) so thateach of their upper surfaces end at the upper surface of the secondinsulating layer 25, where a capacitor structure can be built.

[0052]FIG. 20 shows a capacitor 80 formed on the FIG. 18 structure. Thecapacitor 80 includes a first ruthenium oxide conductor layer 81, atantalum oxide dielectric layer 82, and a second ruthenium oxideconductor layer 83. The capacitor is formed so that conductor 81 is incontact with metal conductors 62 and 72. During the anneal step for thefabrication of the first ruthenium oxide conductor 81, the oxygen frontwill start from the first ruthenium oxide conductor 81, and move towardsthe polysilicon plug 50. The oxygen front is delayed by oxygen sinkspacers 61, 71, and 64 and will not reach the bottom of the metal layer62, which connects to the barrier layer 52, preventing therefore theformation of a barrier oxide layer, such as oxide layer 53 of FIG. 3.Further steps to create a functional memory cell containing the metaloxide-metal-polysilicon contact (FIGS. 15-20) may now be carried out toform other conductors or structures necessary for memory cellfabrication.

[0053] It should be noted again that the metal used for layers 62 and 72must be one of those in which the metal oxide is conductive. Suitablematerials include platinum, rhodium, ruthenium, and iridium, amongothers.

[0054] A typical processor based system 400 which includes a memorycircuit 448, e.g. a DRAM, containing metal-polysilicon contactsaccording to the present invention is illustrated in FIG. 21. Aprocessor system, such as a computer system, generally comprises acentral processing unit (CPU) 444, such as a microprocessor, a digitalsignal processor, or other programmable digital logic device, whichcommunicates with an input/output (I/O) device 446 over a bus 452. Thememory 448 communicates with the central processing unit 444 over bus452.

[0055] In the case of a computer system, the processor system mayinclude peripheral devices such as a floppy disk drive 454 and a compactdisk (CD) ROM drive 456 which also communicate with CPU 444 over the bus452. Memory 448 is preferably constructed as an integrated circuit,which includes metal-polysilicon contacts formed as previously describedwith respect to the embodiments described in connection with FIGS. 4 to20. The memory 448 may also be combined with the processor, e.g. CPU444, on a single integrated circuit chip. It is also possible to employthe invention in metal-polysilicon contacts within said processor.

[0056] Although the exemplary embodiments described above refer to oneor two oxygen sink spacers and oxygen sink layers, and one or two metallayers for the formation of the metal oxide-metal-polysilicon contact(FIGS. 15-20), it is to be understood that the present inventioncontemplates the use of a plurality of oxygen sink spacers, oxygen sinklayers, and metal layers, and it is not limited by the illustratedembodiments. Accordingly, the above description and drawings are only tobe considered illustrative of exemplary embodiments which achieve thefeatures and advantages of the present invention. Modification andsubstitutions to specific process conditions and structures can be madewithout departing from the spirit and scope of the present invention.Accordingly, the invention is not to be considered as being limited bythe foregoing description and drawings, but is only limited by the scopeof the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A metal-polysilicon contact providingelectrical connection on a substrate, said metal-polysilicon contactcomprising: a polysilicon layer; a barrier layer formed over saidpolysilicon layer; at least one conductive layer formed over saidbarrier layer; and at least one oxygen sink layer formed adjacent tosaid conductive layer, said oxygen sink layer being capable of absorbingoxygen.
 2. The metal-polysilicon contact of claim 1, wherein saidconductive layer is formed in an opening of an insulating layer, saidconductive layer having at least one vertically extending surface insaid opening.
 3. The metal-polysilicon contact of claim 2, wherein saidoxygen sink layer contacts said conductive layer at said at least onevertically extended surface.
 4. The metal-polysilicon contact of claim1, wherein said conductive layer is made of a material which isconductive when oxidized.
 5. The metal-polysilicon contact of claim 1,wherein said conductive layer comprises a platinum layer.
 6. Themetal-polysilicon contact of claim 1, wherein said conductive layercomprises a platinum oxide layer.
 7. The metal-polysilicon contact ofclaim 1, wherein said conductive layer comprises an iridium layer. 8.The metal-polysilicon contact of claim 1, wherein said conductive layercomprises an iridium oxide layer.
 9. The metal-polysilicon contact ofclaim 1, wherein said conductive layer comprises a ruthenium layer. 10.The metal-polysilicon contact of claim 1, wherein said conductive layercomprises a ruthenium oxide layer.
 11. The metal-polysilicon contact ofclaim 1, wherein said conductive layer comprises a rhodium layer. 12.The metal-polysilicon contact of claim 1, wherein said conductive layercomprises a rhodium oxide layer.
 13. The metal-polysilicon contact ofclaim 1, wherein said barrier layer is formed of a material selectedfrom the group consisting of refractory metal nitrides, refractory metalcarbides, and refractory metal borides.
 14. The metal-polysiliconcontact of claim 1, wherein said barrier layer is formed of TiSi₂. 15.The metal-polysilicon contact of claim 1, wherein said barrier layer hasa thickness of approximately 60 to 200 Angstroms.
 16. Themetal-polysilicon contact of claim 1, wherein said conductive layer hasa thickness of approximately 100 to 300 Angstroms.
 17. Themetal-polysilicon contact of claim 1, wherein said oxygen sink layer isformed of a material selected from the group consisting of polysilicon,aluminum nitride, titanium nitride, tantalum, and silicon nitride. 18.The metal-polysilicon contact of claim 1, wherein said oxygen sink layeris formed of titanium.
 19. The metal-polysilicon contact of claim 1further comprising a capacitor formed over and in contact with saidconductive layer.
 20. The metal-polysilicon contact of claim 1, whereinsaid metal-polysilicon contact is a high aspect ratio contact.
 21. Themetal-polysilicon contact of claim 20, wherein said high aspect ratiocontact has an aspect ratio of at least
 25. 22. The metal-polysiliconcontact of claim 1, wherein said metal-polysilicon is part of a memorycircuit.
 23. The metal-polysilicon contact of claim 1, wherein saidsubstrate is a semiconductor substrate.
 24. The metal-polysiliconcontact of claim 23, wherein said semiconductor substrate is a siliconsubstrate.
 25. The metal-polysilicon contact of claim 23, wherein saidsemiconductor substrate is a germanium substrate.
 26. Themetal-polysilicon contact of claim 23, wherein said semiconductorsubstrate is a gallium arsenide substrate.
 27. The metal-polysiliconcontact of claim 1, wherein said at least one oxygen sink layercomprises a plurality of spaced oxygen sink layers.
 28. Themetal-polysilicon contact of claim 27, wherein said plurality of spacedoxygen sink layers comprises two oxygen sink layers separated by oneconductive layer.
 29. The metal-polysilicon contact of claim 27, whereinsaid plurality of oxygen sink layers comprises three spaced oxygen sinklayers separated by two contacting conductive layers.
 30. Themetal-polysilicon contact of claim 1 further comprising at least oneoxygen barrier layer provided between said oxygen sink layer and saidconductive layer.
 31. The metal-polysilicon contact of claim 30, whereinsaid oxygen barrier layer is formed of silicon nitride.
 32. Themetal-polysilicon contact of claim 31, wherein said oxygen sink layer isformed of titanium.
 33. A method for fabricating a metal-polysiliconcontact in a semiconductor device, comprising the steps of: forming aninsulating layer over a barrier layer residing over a polysilicon layer;forming a contact opening in said insulating layer; and forming at leastone conductive layer and at least one oxygen sink layer in said contactopening, said oxygen sink layer being capable of absorbing oxygen. 34.The method of claim 33, wherein said conductive layer is formed adjacentto said oxygen sink layer.
 35. The method of claim 33, wherein saidconductive layer is formed of a material which is conductive whenoxidized.
 36. The method of claim 33, wherein said conductive layercomprises a platinum layer.
 37. The method of claim 33, wherein saidconductive layer comprises a platinum oxide layer.
 38. The method ofclaim 33, wherein said conductive layer comprises an iridium layer. 39.The method of claim 33, wherein said conductive layer comprises aniridium oxide layer.
 40. The method of claim 33, wherein said conductivelayer comprises a ruthenium layer.
 41. The method of claim 33, whereinsaid conductive layer comprises a ruthenium oxide layer.
 42. The methodof claim 33, wherein said conductive layer comprises a rhodium layer.43. The method of claim 33, wherein said conductive layer comprises arhodium oxide layer.
 44. The method of claim 33, wherein said barrierlayer is formed of a material selected from the group consisting ofrefractory metal nitrides, refractory metal carbides, and refractorymetal borides.
 45. The method of claim 33, wherein said barrier layer isformed of TiSi₂.
 47. The method of claim 33, wherein said barrier layerhas a thickness of approximately 60 to 200 Angstroms.
 48. The method ofclaim 33, wherein said metal layer has a thickness of approximately 100to 300 Angstroms.
 49. The method of claim 33, wherein said oxygen sinklayer is formed of a material selected from the group consisting ofpolysilicon, aluminum nitride, titanium nitride, tantalum, and siliconnitride.
 50. The method of claim 33, wherein said oxygen sink layer isformed of titanium.
 51. The method of claim 33, wherein said at leastone oxygen sink layer is formed as a plurality of spaced oxygen sinklayers.
 52. The method of claim 51, wherein said plurality of spacedoxygen sink layers comprises two oxygen sink layers separated by oneconductive layer.
 53. The method of claim 51, wherein said plurality ofspaced oxygen sink layers comprises three oxygen sink layers separatedby two contacting conductive layers.
 54. The method of claim 33 furthercomprising at least one oxygen barrier layer provided between saidoxygen sink layer and said conductive layer.
 55. The method of claim 54,wherein said oxygen barrier layer is formed of silicon nitride.
 56. Themethod of claim 55, wherein said oxygen sink layer is formed oftitanium.
 57. The method of claim 33, wherein said step of forming saidbarrier layer includes sputtering.
 58. The method of claim 33, whereinsaid step of forming said contact opening includes etching of saidinsulating layer.
 59. The method of claim 33, wherein said step offorming said at least one oxygen sink layer includes sputtering.
 60. Themethod of claim 33 further comprising the step of forming asemiconductor device over said metal-polysilicon contact.
 61. The methodof claim 60, wherein said semiconductor device is a capacitor.
 62. Themethod of claim 60, wherein said semiconductor device is part of anintegrated circuit.
 63. A processor-based system, comprising: aprocessor; and a memory circuit coupled to said processor, at least oneof said processor and said memory circuit containing a metal-polysiliconcontact, said metal-polysilicon contact comprising a polysilicon layerformed over a substrate; a barrier layer formed over said polysiliconlayer; at least one conductive layer formed over said barrier layer; andat least one oxygen sink layer formed adjacent to said conductive layer,said oxygen sink layer being capable of absorbing oxygen.
 64. Theprocessor-based system of claim 63, wherein said conductive layer isformed in an opening of an insulating layer, said conductive layerhaving at least one vertically extended surface in said opening.
 65. Theprocessor-based system of claim 63, wherein said oxygen sink layercontacts said conductive layer at said at least one vertically extendedsurface.
 66. The processor-based system of claim 63, wherein saidconductive layer is made of a material which is conductive whenoxidized.
 67. The processor-based system of claim 63, wherein saidconductive layer comprises a platinum layer.
 68. The processor-basedsystem of claim 63, wherein said conductive layer comprises a platinumoxide layer.
 69. The processor-based system of claim 63, wherein saidconductive layer comprises an iridium layer.
 70. The processor-basedsystem of claim 63, wherein said conductive layer comprises an iridiumoxide layer.
 71. The processor-based system of claim 63, wherein saidconductive layer comprises a ruthenium layer.
 72. The processor-basedsystem of claim 63, wherein said conductive layer comprises a rutheniumoxide layer.
 73. The processor-based system of claim 63, wherein saidconductive layer comprises a rhodium layer.
 74. The processor-basedsystem of claim 63, wherein said conductive layer comprises a rhodiumoxide layer.
 75. The processor-based system of claim 63, wherein saidbarrier layer is formed of a material selected from the group consistingof refractory metal nitrides, refractory metal carbides, and refractorymetal borides.
 76. The processor-based system of claim 63, wherein saidoxygen sink layer is formed of a material selected from the groupconsisting of polysilicon, aluminum nitride, titanium nitride, tantalum,and silicon nitride.
 77. The processor-based system of claim 63 furthercomprising a capacitor formed over and in contact with said conductivelayer.
 78. The processor-based system of claim 63, wherein saidmetal-polysilicon contact is a high aspect ratio contact.
 79. Theprocessor-based system of claim 63, wherein said high aspect ratiocontact has an aspect ration of at least
 25. 80. The processor-basedsystem of claim 63, wherein said substrate is a semiconductor substrate.81. The processor-based system of claim 80, wherein said semiconductorsubstrate is a silicon substrate.
 82. The processor-based system ofclaim 80, wherein said semiconductor substrate is a germanium substrate.83. The processor-based system of claim 80, wherein said semiconductorsubstrate is a gallium arsenide substrate.
 84. The processor-basedsystem of claim 63, wherein said metal-polysilicon contact is part ofsaid processor.
 85. The processor-based system of claim 63, wherein saidmetal-polysilicon contact is part of said memory circuit.
 86. A memorycell, comprising: a substrate; a transistor including a gate fabricatedon said substrate and including a source/drain region in said substratedisposed adjacent to said gate; a capacitor including an electrode, saidelectrode having a surface aligned over said source/drain region; and ametal-polysilicon structure providing electrical contact between saidsource/drain region and said surface of said electrode, saidmetal-polysilicon structure comprising a polysilicon layer formed oversaid substrate; a barrier layer formed over said polysilicon layer; atleast one conductive layer formed over said barrier layer; and at leastone oxygen sink layer formed adjacent to said conductive layer, saidoxygen sink layer being capable of absorbing oxygen.
 87. The memory cellof claim 86, wherein said conductive layer is formed in an opening of aninsulating layer, said conductive layer having at least one verticallyextended surface in said opening.
 88. The memory cell of claim 86,wherein said oxygen sink layer contacts said conductive layer at said atleast one vertically extended surface.
 89. The memory cell of claim 86,wherein said conductive layer is made of a material which is conductivewhen oxidized.
 90. The memory cell of claim 86, wherein said conductivelayer comprises a platinum layer.
 91. The memory cell of claim 86,wherein said conductive layer comprises a platinum oxide layer.
 92. Thememory cell of claim 86, wherein said conductive layer comprises aniridium layer.
 93. The memory cell of claim 86, wherein said conductivelayer comprises an iridium oxide layer.
 94. The memory cell of claim 86,wherein said conductive layer comprises a ruthenium layer.
 95. Thememory cell of claim 86, wherein said conductive layer comprises aruthenium oxide layer.
 96. The memory cell of claim 86, wherein saidconductive layer comprises a rhodium layer.
 97. The memory cell of claim86, wherein said conductive layer comprises a rhodium oxide layer. 98.The memory cell of claim 86, wherein said barrier layer is formed of amaterial selected from the group consisting of refractory metalnitrides, refractory metal carbides, and refractory metal borides. 99.The memory cell of claim 86, wherein said oxygen sink layer is formed ofa material selected from the group consisting of polysilicon, aluminumnitride, titanium nitride, tantalum, and silicon nitride.
 100. Thememory cell of claim 86, wherein said oxygen sink layer is formed oftitanium.
 101. The memory cell of claim 86 further comprising acapacitor formed over and in contact with said conductive layer. 102.The memory cell of claim 86, wherein said metal-polysilicon contact is ahigh aspect ratio contact.
 103. The memory cell of claim 86, whereinsaid high aspect ratio contact has an aspect ratio of at least
 25. 104.The memory cell of claim 86, wherein said substrate is a semiconductorsubstrate.
 105. The memory cell of claim 86, wherein said semiconductorsubstrate is a silicon substrate.
 106. The memory cell of claim 86,wherein said semiconductor substrate is a germanium substrate.
 107. Thememory cell of claim 86, wherein said semiconductor substrate is agallium arsenide substrate.
 108. The memory cell of claim 86, whereinsaid at least one oxygen sink layer comprises a plurality of spacedoxygen sink layers.
 109. The memory cell of claim 108, wherein saidplurality of spaced oxygen sink layers comprises two oxygen sink layersseparated by one conductive layer.
 110. The memory cell of claim 108,wherein said plurality of spaced oxygen sink layers comprises threeoxygen sink layers separated by two contacting conductive layers.